Modern computing systems have become increasingly more powerful because integrated circuit (IC) chips within these computer systems are operating at increasingly faster clock frequencies. At the same time, these IC chips also consume more power due to these faster clock frequencies. However, in many computing environments, it is desirable to reduce power consumption, for example, in mobile computing systems.
Clock frequencies used by a wide range of electronic systems, such as mobile phones, laptop computers, tablets, and GPS are often generated by a phase-locked loop (PLL) frequency synthesizer. A PLL frequency synthesizer can combine frequency multiplication, frequency division, and frequency mixing operations to produce a wide range of desired clock frequencies.
In common PLL frequency synthesizer designs, one or more frequency dividers are often included in the feedback path of a PLL frequency synthesizer. In particular, to obtain fine granularity of fractional frequencies, multiple frequency dividers or multi-modulus dividers are often used. This type of PLL frequency synthesizers includes sigma-delta modulator (SDM)-based fractional-N PLL frequency synthesizers (see FIG. 1) and phase interpolator (PI)-based fractional-N PLL frequency synthesizers (see FIG. 2). Both SDM-based PLL frequency synthesizers and PI-based PLL frequency synthesizers require using one or more frequency dividers to generate feedback clock signals. In applications where frequency division value N is high, multiple stages of frequency dividers are often required, which leads to high power consumption and noise contribution from these frequency dividers.